1. Field of the Invention
The present invention relates to the design of integrated circuits. More specifically, the present invention relates to a method and an apparatus for placing repeating flip-flop stations on signal lines within an integrated circuit.
2. Related Art
Modern integrated circuits include many functional blocks such as arithmetic-logic units, cache memory units, I/O units, and the like. After these functional blocks have been placed on the floor plan of the integrated circuit, the functional blocks are interconnected through signal lines to allow signals to flow between the functional blocks.
During this interconnection process, the signal paths must be kept short so that the transit time for a signal does not exceed one clock cycle. On signal paths that are longer than one clock cycle, one or more flip-flops need to be placed in the signal path to divide the signal path into multiple segments, wherein each segment takes less than one clock cycle to traverse.
FIG. 1 illustrates the process of segmenting a signal path on an integrated circuit 102. Integrated circuit 102 includes functional blocks 104, 106, 108, 110, and 112. Integrated circuit 102 also includes repeater stations 114, 116, 118, 120, 122, 124, 126, and 128, which can be used to provide fan-out for signals between functional blocks 104, 106, 108, 110, and 112 and for other purposes. Note that repeater stations 114, 116, 118, 120, 122, 124, 126, and 128 are located in channels 130.
As illustrated by the dashed line in FIG. 1, a signal source 111 in functional block 112 is interconnected with a signal receiver 107 in functional block 106. Because this signal path is greater than one clock cycle, the signal path is split into segments 132 and 134, which each have a delay less than one clock cycle. Flip-flop 133 is used to couple segment 132 to segment 134. However, since flip-flop 133 is placed within functional block 104 the register transfer language (RTL) source for functional block 104 must be changed. This is undesirable because within functional block 104 many elements can be affected, which can require adjustments to timing and placement of critical elements. Additionally, since integrated circuit clock speeds are continuing to increase and integrated circuit sizes are continuing to increase, it is becoming increasingly more difficult to place the repeating flip-flops into functional blocks while still providing segments with less than one cycle delay.
Hence, what is needed is a method and an apparatus that allows flip-flops to be placed on signal paths without the problems described above.